1. Field of the Invention
This disclosure relates to semiconductor devices, and more particularly, to a vertical transistor structure having a vertical-type gate and to a method of forming the same.
2. Description of the Related Art
Requirements for semiconductor devices with lower electricity consumption and higher capacitance have prompted researchers to develop higher integrated and higher speed semiconductor devices. In particular, a semiconductor memory cell, a DRAM (Dynamic Random Access Memory), has been used widely, and research is focused on ways to enhance the speed and integration of this device.
In general, a DRAM is constructed of one MOS (Metal Oxide Semiconductor) transistor and one storage capacitor. The MOS transistor is incorporated to move charges from a storage capacitor while writing and reading data, the data being represented by the charges. The DRAM also performs a refresh operation by periodically providing charge to the storage capacitor to prevent data loss caused by leakage current, etc.
To obtain a high integration of DRAM, a capacitor capable of sufficiently guaranteeing a storage capacitance even if a storage capacitance size is reduced, is required, and it needs to substantially reduce an occupied area of a unit memory cell. A manufacturing of a general DRAM device is limited by a minimum lithography feature size (F) by a photolithography process. According to the conventional art, the size of a DRAM cell is equal to the square of the given lithography feature size (F) multiplied by a coefficient of eight (8F2). A DRAM device, in which a unit memory cell as a planar type transistor has an (8F2) structure, is disclosed in U.S. Pat. No. 5,900,659 with the title of “Buried bit line DRAM cells”. A DRAM device, in which a unit memory cell as a recess type transistor has an (8F2) structure, is disclosed in U.S. Pat. No. 6,555,872 with the title of “TRENCH GATE FERMI-THRESHOLD FIELD EFFECT TRANSISTORS”. A DRAM device, in which a unit memory cell as a fin type transistor has an (8F2) structure, is disclosed in U.S. Pat. No. 6,525,403 with the title of “SEMICONDUCTOR DEVICE HAVING MIS FIELD EFFECT TRANSISTORS OR THREE-DIMENSIONAL STRUCTURE”.
FIG. 1 is a plan view of a layout structure of a MOS transistor according to a prior art.
With reference to FIG. 1, two gate electrodes 130 having a predetermined thickness are formed in a vertical direction on an active region 120 surrounded by a non-active region 110. A contact 150 connected to a bit line is formed on the active region between the gate electrodes 130. A contact 160 connected to a storage node is formed in both side faces of the gate electrodes, and a bit line 140 is disposed in a horizontal direction between the active regions.
According to a related art, since two gate electrodes are formed with a predetemined thickness on one active region and contacts arc formed between the gate electrodes, a gate electrode and a contact occupy a specific horizontal area. Thus, a unit memory cell 170 has an (8F2) structure and this is applied equally to a planar type transistor, a recess type transistor and a fin type transistor. Hence, obtaining a highly-integrated semiconductor device has difficulties and limitations, in particular to integrate beyond a given level.